DisplayPort is a new graphics communications interface that seeks to do for the PC what HDMI did for the TV -- display HD video content. And as with HDMI, there are unique protection issues with DisplayPort designs, stemming from the high-speed of the interface and the constant threat of electro static and cable discharge events from normal use.
The DisplayPort standard is an uncompressed, open digital communication interface that represents a cost reduction opportunity for PC makers by consolidating the internal and external interconnect. When used internally, it is an interface within a PC or monitor. Externally, it connects a PC to a monitor or projector, or TV. When used as an external interface, the DisplayPort plug is frequently exposed to electrostatic discharge (ESD) directly from the user or cable discharge (CDE) from hot plug cable.
To ensure proper functionality, DisplayPort-based systems must protect all potentially exposed interface signals and power pins to meet or exceed the EOS (electrical over stress) specification of IEC 61000-4-2, Level 4 (+/- 15kV Air, +/-8kV Contact) without damage.
In most cases, the on-chip ESD protection is no longer sufficient to meet this EOS requirement, making off chip ESD protection circuitry necessary for EOS compliance. Providing this protection is further complicated by the high-speed of the link rates; both 2.7Gbps and 1.62Gbps are supported in the standard. At such a high data rate, signal integrity and impedance requirements are given more focus than ever before, as put forth in the DisplayPort Compliant Test Specification (CTS).
Note: A more detailed description of the DisplayPort standard appears on the last page.
The ESD/CDE landscape:
Increasing ESD/CDE events, decreasing on-chip protection
Interface ESD protection has become increasingly difficult as the industry moves along its current process technology trajectory. Simultaneous demands for faster processing speed and higher functional density have resulted in further shrinkage of the minimum dimensions of MOS devices. In early 2007, Intel introduced its first processor prototypes based on a 45-nanometer technology. However, as IC chips grow smaller, denser, and more complex, they become more susceptible to ESD events.
On-chip ESD shunting structures were traditionally employed to protect the inner circuitry from ESD strikes; yet, they are increasingly sacrificed in favor of performance as the geometries continue to shrink making chip real estate more valuable.
In August 2007, the Industry Council on ESD Target Levels released a proposal to lower on-chip IC ESD target levels from 2kV HBM (Human Body Model) / 200V MM (Machine Model) to 1kV HBM / 30V MM to facilitate the industry's ability to design and quickly bring to market high-speed and high-performance ICs. In the meantime, the system level ESD target levels remain at 8kV contact / 15kV air discharge as put forth in IEC 61000-4-2. Therefore, while carefully designed on-chip ESD structures may still serve as excellent secondary protection, sufficient standards-compliant protection can only be realized with robust off-chip solutions.
Another reason why off-chip protection is necessary and important has a lot to do with the placement of the protection element. Normally the on-chip protection circuitry resides too far away from the interface entry point. When ESD-induced transients travel, they can be coupled into nearby traces including data lines, clock signal lines, and power lines. What is more, the magnitude of their voltage is increased due to the Ldi/dt effect (Vpk=Vesd + Ldi/dt).
Cable discharge
I/O applications -- like DisplayPort -- are subject to another common type of ESD known as cable discharge (CDE). It occurs when a charged cable is plugged into its receptacle and the difference in the potential causes a sudden discharge into the circuit that can cause damage to the IC. Simply pulling a cable out of its packing can make it charged, not to mention dragging it along the carpet to accumulate more charges. There is not yet an established CDE standard, but significant efforts have been made to address this both on the system level and component level. Currently, the common practice in the industry is to test the system per IEC standard.
Next: Human Body Model (HBM), Machines Model (MM) and Charged Device Model (CDM)
|
